ERC Starting Grant

Multifunctional surface nano-patterns on substrates are the foundation of semiconductor nano-devices. There is a major shortcoming of the existing surface nano-patterning techniques - in fact almost all synthesized surface patterns are two-dimensional (2-D) planar structures with low aspect ratio. Thus one of the most attractive advantages of nanomaterials, an extremely large surface area, is missing in the existing 2-D surface nano-patterns. This largely limits the application potential of surface nanostructures on semiconductor devices. In this project, a new concept of three-dimensional (3-D) nano-patterning is proposed. Using this multi-functional 3-D surface nano-patterning technique, large-scale surface patterns of well-defined one-dimensional (1-D) nanostructures can be synthesized by different fabrication strategies. The realization of the 3-D surface nano-patterning will not only retain the attractive features of the conventional 2-D surface nano-patterning (e.g. high patterning density), but also bring back one of the basic advantages of nanomaterials, i.e. an extremely large surface area. Using an innovative addressing system proposed in this project, it is possible to investigate and analyze the properties of an individual unit within a regular surface nanostructure array and the coupling interaction between the adjacent units. By integrating these data, the properties of the whole ensembles could be obtained. This bottom-up investigation might pave the way to a complete property tuning based on the structural design of surface 1-D nanostructures. The large-scale 1-D surface nano-patterns with well-defined structures have broad application potentials for different high-performance and property-controllable nano-devices.